The present invention relates to a shift register which is preferably applied to, for example, a driving circuit of an image display device, and which makes it possible to miniaturize the driving circuit and also to desirably change the pulse width of an output signal, and also concerns an image display device using such a shift register.
Conventionally, in a data signal line driving circuit and a scanning signal line driving circuit of an image display device, shift registers have been widely used so as to provide synchronized timing that is applied upon sampling inputted video image data, or so as to form a scanning signal to be applied to the scanning signal lines.
In the data signal line driving circuit, a sampling signal is generated so as to write video image data derived from a video image signal in pixels through a data signal line. In this case, when a sampling signal has an overlapped portion with a sampling signal from the preceding stage or the succeeding stage, the resulting video image data fluctuates greatly, causing erroneous image data to be outputted to the data signal line. In order to solve the above-mentioned problems, a conventional shift register 101 has a circuit construction, for example, as shown in FIG. 32.
The shift register 101, shown in FIG. 32, consists of n stages, and each stage is provided with a D-type flip-flop 102, a NAND circuit 103, inverters 104a and 104b and a NOR circuit 105. To the shift register 101, two clock signals SCKxc2x7SCKB, which have phases different from each other, and a start pulse SSP are inputted.
Each of the clock signals SCKxc2x7SCKB is prepared so as to have half the sampling cycle of the inputted video image signal, and in synchronism with the clock signals SCKxc2x7SCKB, pulses are successively outputted from the shift registers 101 on the respective stages. With respect to the i-numbered stage (1xe2x89xa6ixe2x89xa6n), an output Qixe2x88x921 of the D-type flip-flop 102 on the (ixe2x88x921)-numbered stage and an output Qi of the D-type flip-flop 102 on the i-numbered stage are inputted to the NAND circuit 103 on the i-numbered stage so that an output signal NSouti is obtained.
Moreover, in order to prevent a sampling signal Si on the i-numbered stage and a sampling signal Si+1 on the (i+1)-numbered stage from overlapping each other, the output signal NSOUTi is not only directly inputted to one of the input terminals of the NOR circuit on the i-numbered NOR circuit 105, but also inputted to a delay circuit constituted by inverters 104a and 104b on two steps. Since the output of the delay circuit is inputted to the other input terminal of the NOR circuit 105, it is possible to shorten the width of the sampling signal S1 outputted from the NOR circuit 105 on the i-numbered stage.
The same process as described above is carried out on each of the shift registers 101 on the respective stages so that as illustrated in FIG. 33, sampling signals S1 to Sn having no overlapped portions with each other are obtained.
Next, referring to FIGS. 34 and 35, an explanation will be given of a conventional shift register 111 installed in a scanning signal line driving circuit.
The scanning signal line driving circuit outputs a scanning signal to each of the scanning signal lines so that video image data is successively written in pixels arranged on a display section. At this time, the pulse output has to be stopped so that the (i+1)-numbered scanning signal is not overlapped with the i-numbered scanning signal or so that a process for refreshing the video image data that has been written on the i-numbered data signal line is carried out.
Therefore, as illustrated in FIG. 34, the conventional shift register 111, installed in the scanning signal line driving circuit, consists of n stages, and each stage is provided with a D-type flip-flop 112, a NAND circuit 113 and a NOR circuit 114. Moreover, to the shift register 111, two clock signals GCKxc2x7GCKB, which have phases different from each other, a start pulse GSP and a pulse width control signal PWC are inputted.
In the shift register 111, pulses are successively outputted from the respective stages in synchronism with the clock signals GCKxc2x7GCKB. With respect to the i-numbered stage (1xe2x89xa6ixe2x89xa6n), an output Qi-1 of the D-type flip-flop 112 on the (ixe2x88x921)-numbered stage and an output Qi of the D-type flip-flop 112 on the i-numbered stage are inputted to the NAND circuit 113 on the i-numbered stage so that an output signal NOUTi is obtained. The output signals NOUT1 to NOUTn, thus obtained, are outputted in the same cycles as the respective scanning signals GL1 to GLn.
In the shift register 111, the pulse width control signal PWC is further inputted to one of the input terminals of the NOR circuit 114 on each stage. Moreover, to the other input terminal of the NOR circuit 114 on the i-numbered stage is inputted the output signal NOUTi of the-NAND circuit 113 on the i-numbered stage. Consequently, a scanning signal GLi is outputted from the NOR circuit 114 from the i-numbered stage.
The same process as described above is carried out on each of the shift registers 111 on the respective stages so that as illustrated in FIG. 35, sampling signals GL1 to GLn having no overlapped portions with each other are obtained. Therefore, the (i+1)-numbered scanning signal GLi+1 is not overlapped with the i-numbered scanning signal GLi so that a process for carrying out a refreshing process, etc. on video image data that has been written on the i-numbered data signal is provided.
Here, as illustrated in FIG. 36, in the above-mentioned D-type flip-flops 102xc2x7112, when a signal A is inputted through the D terminal and two clock signals CKxc2x7CKB are inputted through the other terminal, a signal B is outputted from the Q terminal.
However, the conventional shift registers 101xc2x7111 require circuits as shown in FIGS. 32 and 34, resulting in a problem of a bulky driving circuit.
In recent years, there have been ever-increasing demands for image display devices having a wider display screen and a narrower frame width with high precision; therefore, it is necessary to make the area of the driving circuit smaller. Moreover, in applications other than image display devices, there are high demands for simplified circuit construction of shift registers.
Moreover, with respect to a conventional shift register used for a data signal line driving circuit, an arrangement as shown in FIG. 37 is proposed. In the shift register shown in FIG. 37, an S clock signal SCK is applied with a cycle half the sampling cycle of the inputted video image signal, and an output of the shift register section P1S is successively outputted in synchronism with the clock signal.
With respect to an n-numbered stage of the shift register P1S, an output Qn on the n-numbered stage (SSRn) and an output Qnxe2x88x921 on the (nxe2x88x921)-numbered stage (SSRnxe2x88x921) are used in a NAND_Sn so as to obtain NSOUTn.
A sampling signal on the n-numbered stage is allowed to have a narrower sampling signal by using a NOR_San which takes NOR between the NSOUTnand the sampling pulse width control signal SPWC for controlling the sampling pulse width, so as not to overlap the sampling signal on the (nxe2x88x921) stage. The same process is carried out on each of the outputs of the shift registers P1S so that, as illustrated in a timing chart in FIG. 38, a sampling signal having no overlapped portion is obtained. In this case, the pulse width control signal SPWC has a frequency twice the frequency of the S clock signal SCK.
Moreover, with respect to a conventional shift register used for a scanning signal line driving circuit, an arrangement as shown in FIG. 39 is proposed. In the shift register shown in FIG. 39, a scanning signal, writes a video image signal applied to a data signal line on pixels arranged on a display section, is successively outputted. In this case, with respect to the n-numbered scanning signal, its output has to be stopped so that it is not overlapped with the (nxe2x88x921)-numbered scanning signal or so that a process for refreshing the video image data that has been written on the (nxe2x88x921)-numbered data signal line is carried out.
More specifically, referring to a circuit diagram of FIG. 39 and its timing chart of FIG. 40, an explanation will be given of the operation. In FIG. 39, the output of the shift register P1G is successively released in synchronism with a G clock signal GCK. With respect to an n-numbered stage of the shift register P1G, an output (Qn) on the n-numbered stage (GSRn) and an output (Qnxe2x88x921) on the (nxe2x88x921)-numbered stage (GSRnxe2x88x921) are used in a NAND_Gn so as to obtain NOUTn. The NOUTn are respectively outputted with the same cycle as the scanning signal.
As described earlier, with respect to the n-numbered scanning signal, its output has to be stopped so that it is not overlapped with the (nxe2x88x921)-numbered scanning signal or so that a process for refreshing the video image data that has been written on the (nxe2x88x921)-numbered data signal line is carried out or so that a precharging process, etc. is carried out. For this reason, a scanning pulse width control signal GPWC is inputted, and this and NOUTn are used in a NOR_Gn so as to obtain GLn. The GLn forms a scanning signal for driving the n-numbered scanning signal line. At this time, the pulse width control signal GPWC has a frequency twice the frequency of the G clock signal GCK.
Here, in the flip-flop circuit (D-flip-flop) constituting the shift register of FIG. 37 and FIG. 39, as illustrated in FIG. 36, the circuit construction is designed so that, when a signal A is inputted to the D-terminal with two clock signals CK and CKB being inputted through the other terminals, a signal B is outputted.
In general, the power consumption increases in proportion to the frequency, the load capacitance and the square of the voltage. Therefore, for example, in circuits that are connected to an image display device, such as those for generating video image signals for the image display device, or in image display devices, there is a tendency to reduce the driving voltage as small as possible.
For example, in a circuit using monocrystal silicon transistors such as the above-mentioned generation circuit for video image signals, the driving voltage is set to, for example, 5 V or 3.3 V, or a value not more than this value, in most cases.
In contrast, in a circuit using polycrystal silicon thin-film transistors so as to ensure a wider display area, such as pixels, a data signal line driving circuit or a scanning signal line driving circuit, since a difference of threshold voltages between substrates tends to reach as high as several volts (for example, 15 V), the reduction of the driving voltage has not been sufficiently achieved. Therefore, in the case when an input signal lower than the driving voltage of a shift register is inputted to a shift register, a level shifter for voltage-raising the input signal is installed in the shift register. In general, with respect to the input signal for the level shifter, two kinds of signals having two phases are used, and the two kinds of signals have respectively reversed phases.
More specifically, as shown in FIGS. 37 and 39, for example, when an input signal having an amplitude of approximately 5 V is inputted to each of shift registers P1S and P1G, two level shifters Ls of the three in the Figure voltage-raises clock signals SCK and GCK to reach the driving voltage (15 V) of the shift registers P1S and P1G. The outputs of these level shifters Ls are inputted to flip-flops SSR1 to SSRx and GSR1 to GSRx that constitute the shift registers P1S and P1G. In synchronism with the outputs of the level shifters Ls thus applied, the shift registers P1S and P1G are allowed to have respective outputs.
However, in various circuits using conventional shift registers as shown in FIGS. 37 and 39, that is, for example, in a data signal line driving circuit, logical circuits (NOR, etc.) are required so as to prevent the sampling signals from overlapped each other, resulting in a large driving circuit; and for example, in a scanning signal line driving circuit, logical circuits (NOR, etc.) are also required so as to prevent the scanning signals from overlapping each other, resulting in a large driving circuit.
Moreover, each of the above-mentioned pulse width control signals SPWC and GPWC has a frequency that is twice the frequency of each of an S clock signal SCK and a G clock signal GCK, resulting in a greater driving frequency.
Moreover, in the shift registers P1S and P1G, after the clock signals SCK, SCKB (with a phase reversed to SCK) and GCK, GCKB (with a phase reversed to GCK) have been shifted in their levels, they are supplied to respective flip-flops constituting the shift register; therefore, the resulting problem is that the greater the distance between the flip-flops SSR1 to SSRx and the distance between the GSR1 to GSR2, the greater the transmission distance, causing an increase in the power consumption. In other words, as the transmission distance becomes longer, the capacitance of the transmission-use signal lines becomes greater, with the result that the level shifters LS require a greater driving capability, thereby resulting in an increase in the power consumption.
Moreover, as in the case when the driving circuit containing level shifters LS is constructed by using polycrystal silicon thin-film transistors, when the level shifter LS has only an insufficient capability, a buffer BUF having a great driving capability needs to be installed immediately after the level shifter LS so as to transmit signal waveaforms that are free from rounding; this further causes an increase in the power consumption.
In recent years, there have been ever-increasing demands for image display devices with high precision having a wider display screen and narrower portions other than the display area; therefore, the frequency of clock signals has to be increased, and in response to this, it is required that the number of the stages of the shift registers P1S and P1G be increased and that the area of the driving circuit be minimized.
The first objective of the present invention is to provide a shift register which has output pulses on respective stages that are free from overlapped portions and which makes it possible to miniaturize the driving circuit and also to desirably change the pulse width of an output signal, and an image processing apparatus which can achieve a narrower frame width with the driving circuit simplified by applying such a shift register.
Moreover, the second objective of the present invention is to provide a shift register which can achieve a narrower frame width by simplifying the driving circuit, and is operated normally even in the case of a low amplitude of a clock signal with reduced power consumption, and an image display device using such a shift register.
In order to achieve the first objective, the shift register of the present invention is provided with: flip-flops of a plurality of stages to which a clock signal is inputted and switching means that is installed in each of the flip-flops of a plurality of stages and that controls the input of the clock signal. In this arrangement, in response to the output signal of the flip-flop on the i-numbered stage (where i is an arbitrary integer) among the flip-flops of the stages, the switching means on the (i+1)-numbered stage is controlled so that the input of the clock signal to the flip-flop on the (i+1)-numbered stage is controlled and an output pulse having the same width as the pulse width of the clock signal is generated.
In the above-mentioned shift register, the output of the flip-flop that is operated in synchronism with the clock signal controls the clock signal to be supplied to the flip-flop on the next stage through the switching means. Here, this controlled clock signal forms an output on the corresponding stage, and the output is allowed to have the same pulse width as the clock signal.
Conventionally, the output of the flip-flop on the preceding stage and the output of that of the present stage have been subjected to a logical operation so as to generate a signal having the same pulse width as the clock signal; however, in the shift register of the present invention, it is not necessary to install the circuit for carrying out the above-mentioned logical operation. Moreover, in the logical operation section, the output from the logical operation section tends to have a partially overlapped portion due to delay (delay in the rising-edge or trailing-edge of the signal) of signals occurring in the logical operation section; however, the shift register of the present invention makes it possible to eliminate the partially overlapped portion of the output of the logical operation section. Furthermore, it is possible to eliminate a special circuit and a transmission line for a special signal for preventing the overlapped portion of the output pulse; therefor, it becomes possible to greatly reduce the size of the shift register.
Therefore, it is possible to provide a shift register which has no overlapped portion in the output pulses from the respective stages and which achieves a simplified circuit construction.
Moreover, in order to achieve the first objective, the image display device of the present invention, which is provided with a display section constituted by a plurality of pixels arranged in a matrix format, a data signal line driving circuit, connected to a plurality of data signal lines, for supplying to the respective data signal lines image data to be written in the pixels, and a scanning signal line driving circuit, connected to a plurality of scanning signal lines, for supplying to the scanning signal lines a scanning signal for controlling a writing operation of the image data to the pixels, is characterized in that the shift register of the present invention is installed at least in either the data signal line driving circuit or the scanning signal line driving circuit.
In the above-mentioned image display device, the application of the shift register of the present invention makes it possible to minimize the circuit scale of the driving circuit and consequently to provide an image processing apparatus which can achieve a narrower frame width.
Moreover, in order to achieve the second objective, the shift register of the present invention, which is provided with flip-flops of a plurality of stages that operate in synchronism with clock signals and level shifters for voltage-raising the clock signals to be inputted to the flip-flops on a plurality of stages, is characterized in that the level shifter is installed in each of the flip-flops on a plurality of stages, and in that supposing that n is an integer not less than 1, in accordance with the output signal of the flip-flop on the n-numbered stage, a pulse that is voltage-raised with the same width of the pulse width of the clock signal by the level shifter on the (n+1)-numbered stage is inputted to the flip-flop on the (n+1)-numbered stage, and is also outputted as an output signal of the shift register.
For example, the present shift register is provided with flip-flops of a plurality of stages that operate in synchronism with clock signals, level shifters, each of which, in the case when the clock signal has a voltage value lower than the power supply voltage, voltage-raises the clock signal for each of the flip-flops on a plurality of stages, and control means for controlling the operation of the level shifter, each of the level shifters and the control means being placed for each of the flip-flops on a plurality of stages. In this arrangement, in accordance with the output signal of the flip-flop on the n-numbered stage of a plurality of stages, the level shifter is controlled by the control means on the (n+1)-numbered stage and the clock signal is voltage-raised and inputted thereto so that the flip-flop on the (n+1) numbered stage is operated, and a pulse which has been voltage-raised so as to have the same width as the pulse width of the clock signal, is outputted.
In the above-mentioned shift register, the output of each of the flip-flops, which is operated in synchronism with the clock signal, is allowed to activate a level shifter that voltage-raises the clock signal to be supplied to the flip-flop on the next stage; thus, it is possible to activate only one portion of the level shifters installed inside the shift register. This voltage-raised clock signal is allowed to form an output (SL1, etc.) of the shift register, which has the same pulse width as the clock signal.
Conventionally, level shifters are installed outside a shift register, and the clock signal is once voltage-raised to a driving voltage, and this is supplied to a plurality of flip-flops constituting the shift register. Moreover, a large buffer is provided so as to prevent the voltage-raised clock signal from being subjected to rounding and delay due to the capacitance of transmission lines, the gate capacitance of transistors connected thereto, etc.; therefore, due to these capacitances and high electric potential after having been raised, as also described in the Prior Art section, the power consumption increases in accordance with the expression, Power P=Capacitance Cxc3x97Frequency fxc3x97a square of Voltage V, resulting in a great increase in the power consumption of the circuit.
In contrast, in accordance with the construction of the present invention, a low-voltage clock signal is transferred and each flip-flop is installed immediately after a level shifter so that one portion of the level shifter splaced in side the shift register are operated; thus, it becomes possible to greatly reduce the power consumption.
In addition, since it is not necessary to install a circuit (NOR, etc.) for carrying out logical operations, the size of the driving circuit can be reduced. Moreover, in the logical operation section, the output from the logical operation section tends to have a partially overlapped portion due to delay (delay in the rising-edge or trailing-edge of the signal) of signals occurring in the logical operation section; however, the present invention makes it possible to eliminate the partially overlapped portion of the output of the logical operation section. Furthermore, it is possible to eliminate a special circuit and a transmission line for a special signal (SPWC, etc.) for eliminating the overlapped portion of the output pulse; therefore, it becomes possible to greatly reduce the size of the driving circuit.
In order to achieve the second objective, the image display device of the present invention is provided with a display section which is provided with: a plurality of pixels arranged in a matrix format; a plurality of data signal lines placed on the respective columns of the pixels and a plurality of scanning signal lines placed on the respective rows of the pixels and which displays an image on the pixel by a data signal that is sent from the data signal line to each pixel in synchronism with a scanning signal supplied from each scanning signal line so as to form an image; a scanning signal driving circuit for successively supplying scanning signals having different timing from each other to the scanning signal lines in synchronism with a first clock having a predetermined cycle; and a data signal line driving circuit for extracting data signals applied onto the respective pixels on the scanning signal line to which the scanning signal has been applied, from a video image signal that has been successively applied in synchronism with a second clock having a predetermined cycle and is representative of a display state of each pixel, and for outputting the resulting data to each of the data signal lines. In the image display device having the above-mentioned arrangement, at least either the data signal line driving circuit and the scanning signal line driving circuit is provided with either of the above-mentioned shift registers having the first or second clock signal as a clock signal.
For example, the above-mentioned scanning signal driving circuit successively outputs the scanning signal to the scanning signal lines in synchronism with a predetermined timing signal. Further, the data signal line driving circuit successively outputs the video image signal to the data signal lines in synchronism with a predetermined timing signal.
In general, in the image display device, as the number of data signal lines or the number of scanning signal lines increases, the number of the flip-flops for generating timing for each signal line increases, thereby making the distance between the two ends of the flip-flop longer. Here, in the shift register of each of the above-mentioned arrangements, the driving capability of the level shifter is small, and even when the distance between the two ends of the flip-flop is long, it is possible to eliminate a buffer, and consequently to reduce the power consumption. Therefore, by installing the shift register having any one of the above-mentioned arrangements in at least either the data signal line driving circuit or the scanning signal line driving circuit, it is possible to reduce the power consumption, to miniaturize the circuit scale of the shift register and also to provide a narrower frame width in the image display device.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.